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71M6521DE/DH/FE Data Sheet
Special Function Registers for the WD Timer
Interrupt Enable 0 Register ( IEN0 ):
MSB
LSB
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
Table 27: The IEN0 Register (see also Table 32)
Bit
IEN0.6
Symbol
WDT
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is
set to prevent an unintentional refresh of the watchdog timer. WDT is reset by
hardware 12 clock cycles after it has been set.
Table 28: The IEN0 Bit Functions (see also Table 32)
Note: The remaining bits in the IEN0 register are not used for watchdog control
Interrupt Enable 1 Register ( IEN1 ):
MSB
LSB
EXEN2
SWDT
EX6
EX5
EX4
EX3
EX2
Table 29: The IEN1 Register (see also Tables 30/31)
Bit
IEN1.6
Symbol
SWDT
Function
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog timer. When directly set after setting WDT , a
watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock
cycles after it has been set.
Table 30: The IEN1 Bit Functions (see also Tables 30/31)
Note: The remaining bits in the IEN1 register are not used for watchdog control
Interrupt Priority 0 Register ( IP0 ):
MSB
LSB
--
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Table 31: The IP0 Register (see also Table 45)
Rev 3
Page: 29 of 107
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